Semiconductor wafer transportation

ABSTRACT

A wafer transportation pod includes a body, a main compartment enclosed by the body, the main compartment to provide a controlled environment, a holding device within the main compartment, the holding device to hold a plurality of semiconductor wafers, a top latching mechanism configured to connect to another pod or a carrier mechanism of an overhead hoist transfer (OHT) system, a bottom latching mechanism configured to connect to another pod, the bottom latching mechanism being similar to the latching mechanism on the carrier.

BACKGROUND

In semiconductor technologies, a semiconductor wafer is processed through various fabrication steps to form integrated circuits defined in multiple chips. Those fabrication steps include lithography patterning, etching, ion implantation, deposition, oxidation and thermal annealing. Different tools are used to perform these different types of processes on semiconductor wafers. Thus, the wafers must be transferred between tools after each process is performed.

It is generally desirable to avoid human contact with the semiconductor wafers as they are transferred because various contaminants or static discharges may harm the wafers. Thus, wafer transportation pods such as front opening universal pods (FOUPs), which provide a controlled environment, are used to move the semiconductor wafers throughout the fabrication facility to different tools. Robotic mechanisms are used to remove semiconductor wafers and insert them into the fabrication tools.

In some cases, the FOUPs are transported through the fabrication facility by an overhead hoist transfer (OHT) system. The OHT includes several tracks above the ground. A carrier device moves along the tracks and can be lowered to pick up or drop off FOUPs as needed. In order to improve the efficiency of semiconductor fabrication, it is desirable to find ways to increase the efficiency of FOUP transportation.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a diagram showing an illustrative carrier of an OHT that holds more than one semiconductor wafer transportation pod, in accordance with some embodiments.

FIG. 2 is a diagram showing an illustrative semiconductor wafer transportation pod having a top latch and a bottom latch, in accordance with some embodiments.

FIGS. 3A and 3B are diagrams showing illustrative top views of multiple semiconductor wafer transportation pods, in accordance with some embodiments.

FIG. 4 is a diagram showing an illustrative computing system to run an automated material handling system (AMHS), in accordance with some embodiments.

FIG. 5 is a flowchart showing an illustrative method for semiconductor wafer transportation, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG. 1 is a diagram showing an illustrative carrier of an OHT that holds more than one semiconductor wafer transportation pod, or FOUP 106, 108, 110. According to the present example, a carrier 104 is connected to an OHT system 102. The carrier 104 includes a carrier latch 112 that connects to a top latch 114 of a first FOUP 106. The first FOUP 106 has a bottom latch 116 that connects to the top latch 114 of a second FOUP 108. Likewise, a third FOUP 110 is connected to the bottom of the second FOUP 108.

The OHT 102 includes several tracks that run throughout a semiconductor fabrication facility. Typically, these tracks run along, or are suspended from, the ceiling of the facility. The OHT 102 may include several switched tracks on which several carriers 104 can travel. The tracks run between the various locations of fabrication tools. For example, a track might run from an etching tool to an implanting tool or an annealing tool. As such, when the semiconductor wafers finish the etching process, they can be moved by the OHT 102 to the tool for the next step in the fabrication process.

The carrier 104 connects to the track and may be lowered to pick up a FOUP for transportation to the next tool. The carrier 104 thus includes a carrier latch 112 that is designed to latch onto the top of a FOUP 106. Typically, carriers 104 are designed to hold only one FOUP. But, according to principles described herein, the FOUPs 106, 108, 110 can be designed so that multiple FOUPs can be moved by one carrier 104. This increases the efficiency of transportation.

For example, the first FOUP 106 has a bottom latch 116 that matches the carrier latch 112. Thus, the second FOUP 108, which is identical to the first FOUP 106, can user its top latch 114 to connect to the bottom latch 116 of the first FOUP 106. Likewise, the third FOUP 110 can user its top latch 114 to connect to the bottom latch 116 of the second FOUP 108.

FIG. 2 is a diagram showing an illustrative semiconductor wafer transportation pod 200 having a top latch 208 and a bottom latch 210. The semiconductor wafer transportation pod 200 may be, for example, a FOUP 200. The FOUP 200 includes a body 214, a main compartment 212, a door 202, and a holding device 204 to hold semiconductor wafers 206.

As described above, a FOUP is a universal pod used to transport semiconductor wafers 206 through a fabrication facility. The FOUP may have a body 214 made of a variety of materials such as plastic. The body 214 may completely enclose the main compartment 212 in order to provide a controlled environment. The controlled environment is free from various contaminants such as dust particles. Such particles can adversely affect the circuitry being formed on the semiconductor wafers 206.

The front door 202 of the FOUP is designed to engage a controlled environment within a fabrication tool. Thus, once the FOUP 200 is engaged with the tool, a robotic arm within the tool may remove the semiconductor wafers and position them for processes to be performed by that tool. This is done without exposing the semiconductor wafers 206 to an uncontrolled environment that may contain contaminants or static discharges.

The FOUP 200 includes a top latch 208 that is designed to latch onto a carrier latch of a carrier. In some examples, the top latch 208 is positioned at the center of the top side of the FOUP 200. In some examples, a FOUP 200 may include multiple latches on the top to connect to multiple corresponding latches on the bottom side of the carrier. For example, there may be four latches, one on each corner of the top side of the FOUP 200.

The FOUP 200 also includes a bottom latch 210. The bottom latch 210 may match the latch on the carrier. Thus, the bottom latch 210 is configured to connect to the top latch 208 of another similar FOUP. With each FOUP having a standard top latch 208 and bottom latch 210, several similar FOUPs can be connected to a single carrier. Thus, more FOUPs can be transported within a particular time frame.

In one example, the top latch 208 and bottom latch 210 may form a joint that is similar to a tenon and mortise joint. Such a joint includes a peg-like structure (tenon) and a hole-like structure (mortise) into which the peg-like structure fits. In one example, the top latch may be a tenon-like structure and the bottom latch 210, and carrier latch, may be a mortise-like structure.

FIGS. 3A-3B are diagrams showing illustrative top views of multiple semiconductor wafer transportation pods. FIG. 3A illustrates a top view of a first FOUP 302 and a second FOUP 304 before a latching process is complete. According to certain illustrative examples, the latches on the FOUPs may be configured to latch or unlatch based on rotation.

According to the present example, to connect the top latch 308 of the second FOUP 304 to the bottom latch 310 of the first FOUP 302, the top latch 308 may be inserted into the bottom latch 310 of the first FOUP 302 while the second FOUP 304 is at an angle with respect to the first FOUP 302. The top latch 308 of the second FOUP 304 and the bottom latch of the first FOUP 310 are illustrated with dotted lines, indicating that they are not on top of the first FOUP 302. Rather, the top latch 308 and bottom latch 310 are between the first FOUP 302 and the second FOUP 304.

To complete the latching process, after the top latch 308 is inserted into the bottom latch 310 while the FOUPs 302, 304 are at an angle with respect to each other, the carrier 306, which is secured to the first FOUP 302, can rotate. Meanwhile, a loading (or unloading) mechanism 312 secures the second FOUP 304 in place so that it does not rotate. The rotation may continue until the FOUPs 302, 304 are aligned.

FIG. 3B is a diagram showing a top view of the FOUPs 302, 304 after the latching process is complete. Specifically, the first FOUP 302 is now aligned with the second FOUP 304. The carrier 306 can now be raised to transport both FOUPs 302, 304.

In some examples, the carrier 306 may pick up a third FOUP (not shown). This is done in a manner similar to the latching of the first FOUP 302 and second FOUP 304. Specifically, the top latch of the third FOUP is inserted into a bottom latch of the second FOUP 304 while the third FOUP is at an angle with respect to the second FOUP 304. The second FOUP may also remain aligned to the first FOUP 302. The carrier 306 then rotates both the first FOUP 302 and second FOUP 304 to complete the latching process to the third FOUP. Thus, all three FOUPs are aligned and ready for transport.

The unloading/unlatching process is similar to the latching process. Specifically, the carrier 306 may lower the second FOUP 304 into the loading tool 312. The carrier 306 may then rotate while the loading tool 312 secures the second FOUP. Thus, the first FOUP 302 will turn with respect to the second FOUP 304. The rotation will continue until the unlatching process is complete. The carrier 306 can then be raised while the first FOUP 302 is still attached and the second FOUP 304 is left with the loading tool 312.

FIG. 4 is a diagram showing an illustrative computing system to run an automated material handling system (AMHS). According to certain illustrative examples, the processing system 400 includes a memory 404 which may include software 406 and a data store 408. The processing system 400 also includes a processor 410, a network interface 414, and a user interface 412.

The memory 404 may be one of several different types of memory. Some types of memory, such as solid state drives, are designed for storage. These types of memory typically have large storage volume but relatively slow performance. Other types of memory, such as those used for Random Access Memory (RAM), are optimized for speed and are often referred to as “working memory.” The various types of memory may store information in the form of software 406 and data in the data store 408.

The processing system 400 also includes a processor 410 for executing the software 406 and using or updating the data 408 stored in memory 404. The software 406 includes sets of machine readable instructions that when executed by the processor 410, cause the system 400 to perform various tasks. The software 406 may include an operating system and any other software applications a user may wish to install. The software 406 may include machine readable instructions that cause the system 400 to control an AMHS 416.

The software for an AMHS may define what FOUPs are to be picked up at what time and to where they should be transported. An AMHS 416 for a large semiconductor fabrication facility may require careful planning to manage the large volume of FOUPs that need to be transported. Additionally, the software 416 may control the movements of the carriers and loading mechanisms. Thus, the software 416 is programmed to cause the carriers to rotate appropriately in order to latch onto FOUPs. Additionally, the software causes the carriers to latch additional FOUPs onto the bottom of FOUPs already being held by the carriers.

The user interface 412 may include a number of input devices such as a mouse, touchpad, or touchscreen that allow the user 402 to interact with the computing system 400. The user interface 412 may also include a number of different types of output devices such as a monitor or a touchscreen. The user interface allows the user 402 to monitor the status of the AMHS 416 or make adjustments to the AMHS 416 as may be desired.

The network interface 414 may include hardware and software that allows the processing system 400 to communicate with other processing systems over a network 416. The network interface 414 may be designed to communicate with the network 416 through hardwire media such as Ethernet, coaxial, fiber-optic, etc. The network interface 416 may also be designed to communicate with the network 416 using wireless technologies. The network interface 414 allows a user to connect to external databases for purposes of comparing hash results to various databases of hash results.

FIG. 5 is a flowchart showing an illustrative method 500 for semiconductor wafer transportation. According to certain illustrative examples, the method 500 includes a step 502 for causing a carrier of an overhead hoist transfer system (OHT) to latch onto a top latch of a first semiconductor wafer transportation pod, the pod comprising a bottom latch that matches a latch on the carrier. In some examples, the top latch of the first semiconductor wafer transportation pod may connect to the bottom latch of the carrier through rotation.

The method 500 further includes a step 504 for causing the carrier to move the first semiconductor wafer transportation pod such that the bottom latch of the first semiconductor wafer transportation pod latches to a top latch of a second semiconductor wafer transportation pod. This may be done in a manner similar to the carrier latching onto the first semiconductor wafer transportation pod.

To unload the pods, the method may further include a step 506 for causing the carrier to move the first semiconductor wafer pod while the second semiconductor wafer transportation pod is secured to a loading mechanism, thereby unlatching the first semiconductor wafer transportation pod from the second semiconductor wafer transportation pod. Again, this may be done by rotation. The direction of rotation for unlatching is opposite of the direction for latching.

The method 500 may further include a step 508 for causing the carrier to move while the first semiconductor wafer transportation pod is secured to a loading mechanism, thereby unlatching the first semiconductor wafer transportation pod from the carrier. Again, this may be done by rotation.

Systems and methods that utilize principles described herein provide for more efficient semiconductor fabrication. Specifically, by attaching more than one universal transportation pod to a single carrier, more pods can be transferred within a given time frame. This allows for more flexibility in an AMHS design, thus allowing for more efficiency.

According to one embodiment, a wafer transportation pod includes a body, a main compartment enclosed by the body, the main compartment to provide a controlled environment, a holding device within the main compartment, the holding device to hold a number of semiconductor wafers, a top latching mechanism configured to connect to another pod or a carrier mechanism of an overhead hoist transfer (OHT) system, a bottom latching mechanism configured to connect to another pod, the bottom latching mechanism being similar to the latching mechanism on the carrier.

According to one embodiment, a semiconductor wafer pod transportation system includes a carrier mechanism comprising a carrier latch to connect to a top latch of a first semiconductor wafer transportation pod, the first semiconductor wafer pod comprising a body, a main compartment enclosed by the body, the main compartment to provide a controlled environment, a holding device within the main compartment, the holding device to hold a number of semiconductor wafers, and a bottom latch that is similar to the carrier latch.

According to one embodiment, a method for operating an overhead hoist transfer system (OHT) includes causing a carrier of an overhead hoist transfer system (OHT) to latch onto a top latch of a first semiconductor wafer transportation pod, the pod comprising a bottom latch that matches a latch on the carrier, and causing the carrier to move the first semiconductor wafer transportation pod such that the bottom latch of the first semiconductor wafer transportation pod latches to a top latch of a second semiconductor wafer transportation pod.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A wafer transportation pod comprising: a body; a main compartment enclosed by the body, the main compartment configured to provide a controlled environment; a holding device within the main compartment, the holding device to hold a plurality of semiconductor wafers; a top latching mechanism configured to selectively connect to another pod or a carrier mechanism of an overhead hoist transfer (OHT) system; a bottom latching mechanism configured to selectively connect to a top latching mechanism of another pod by rotation of the body of the wafer transportation pod with respect to the other pod.
 2. The wafer transportation pod of claim 1, wherein the pod is configured for use with an Automated Material Handling System (AMHS).
 3. The wafer transportation pod of claim 2, wherein the AMHS is configured to move the semiconductor wafer pod while the other semiconductor wafer transportation pod is secured to a loading mechanism, thereby unlatching the first semiconductor wafer transportation pod from the other semiconductor wafer transportation pod.
 4. The wafer transportation pod of claim 1, wherein the pod comprises a front opening door.
 5. The wafer transportation pod of claim 4, wherein the holding device within the pod is configured to provide the semiconductor wafers thereon to robotic mechanisms that move the semiconductor wafers into fabrication tools.
 6. The wafer transportation pod of claim 1, wherein the top latching mechanism is positioned at a center of a top of the pod.
 7. The wafer transportation pod of claim 6, wherein the top latching mechanism is configured to lock and unlock to the other pod or the carrier by rotation.
 8. The wafer transportation pod of claim 6, wherein the bottom latching mechanism is positioned at a center of a bottom of the pod.
 9. A semiconductor wafer pod transportation system comprising: a carrier mechanism comprising a carrier latch to connect to a top latch of a first semiconductor wafer transportation pod, the first semiconductor wafer pod comprising: a body; a main compartment enclosed by the body, the main compartment to provide a controlled environment; a holding device within the main compartment, the holding device to hold a plurality of semiconductor wafers; and a bottom latch that is configured to attach to a top latch of a second semiconductor wafer transportation pod by rotation of the body of the first semiconductor wafer pod with respect to the second semiconductor wafer transportation pod.
 10. The system of claim 9, further comprising, the second semiconductor wafer transportation pod, the top latch of the second semiconductor wafer transportation pod being attached to the bottom latch of the first semiconductor wafer transportation pod.
 11. The system of claim 10, further comprising, a third semiconductor wafer transportation pod, a top latch of the third semiconductor wafer transportation pod being attached to a bottom latch of the second semiconductor wafer transportation pod.
 12. The system of claim 10, wherein the carrier mechanism is configured to move the first semiconductor wafer pod while the second semiconductor wafer transportation pod is secured to a loading mechanism, thereby unlatching the first semiconductor wafer transportation pod from the second semiconductor wafer transportation pod.
 13. The system of claim 9, further comprising, an Automated Material Handling System (AMHS).
 14. The system of claim 9, wherein the first semiconductor wafer transportation pod comprises a front opening door.
 15. The system of claim 9, wherein the top latch is positioned at a center of a top of the first semiconductor wafer transportation pod.
 16. The system of claim 9, wherein the bottom latch is positioned at a center of a bottom of the first semiconductor wafer transportation pod.
 17. The system of claim 9, wherein the top latch and the bottom latch are rotational latches.
 18. The system of claim 9, wherein the carrier latch is configured to latch to or unlatch from the top latch of the first semiconductor wafer transportation pod by rotation.
 19. A system comprising: a carrier mechanism comprising a carrier latch to connect to a top latch of a first semiconductor wafer transportation pod, the first semiconductor wafer pod comprising: a body; a main compartment enclosed by the body, the main compartment to provide a controlled environment; a holding device within the main compartment, the holding device to hold a plurality of semiconductor wafers; and a bottom latch; and a control system comprising a processor and a memory, the memory comprising machine readable instructions that when executed by the processor, cause the control system to: cause the carrier mechanism to latch onto a top latch of the first semiconductor wafer transportation pod; and cause the carrier mechanism to move the first semiconductor wafer transportation pod such that the bottom latch of the first semiconductor wafer transportation pod latches to a top latch of a second semiconductor wafer transportation pod; wherein the control system is further configured to cause the carrier mechanism to move the first semiconductor wafer pod while the second semiconductor wafer transportation pod is secured to a loading mechanism, thereby unlatching the first semiconductor wafer transportation pod from the second semiconductor wafer transportation pod.
 20. The system of claim 19, wherein the control system is further configured to cause the carrier to move while the first semiconductor wafer transportation pod is secured to a loading mechanism, thereby unlatching the first semiconductor wafer transportation pod from the carrier. 